Variable time delay timers have been known heretofore. For example, A. Brosh U.S. Pat. No. 2,871,419, dated Jan. 27, 1959, shows a variable time delay circuit of the on-delay type that provides a time delay before the energization of a relay that is inversely dependent upon the strength of an incoming carrier signal. This patented circuit has an output voltage characteristic that includes a step voltage pedestal portion and an RC timed ramp portion, the latter being inversely proportional to the strength of an incoming carrier signal. This patented timer is controlled by a noise level input, the stronger the carrier signal the lower the noise level input. Also, the lower the noise level, the higher the pedestal on the voltage characteristic and, therefore, the shorter the time interval that is generated prior to energization of the relay. S. Aviander U.S. Pat. No. 3,431,471, dated Mar. 4, 1969, relates to a static time delay relay that improves the accuracy of the tripping time of the relay by means of a steeper RC circuit voltage slope by maintaining the charging voltage above the capacitor voltage. W. H. Seipp U.S. Pat. No. 3,671,817, dated June 20, 1972, shows a high accuracy solid state timer using an operational amplifier connected as a comparator and having an RC charging network voltage applied to one input of the comparator while an adjustable potentiometer provides a settable comparison voltage, according to the length of time desired, to the other input of the comparator. Thus, the potentiometer may be manually adjusted for selecting the desired length of the time interval. An output relay is energized at the end of the timed interval.
While these prior patented timer systems have been useful for their intended purposes, this invention relates to improvements thereover.